Electronic divider



Dec. 23, 1952 w. WOOD'S'HILL ETAL 2,523,171

ELECTRONIC DIVID'ER Original Filed Ma rch 3, 1950 8.-Sheet's-Shee.t 1

l l iNVENTORS DAVID T. DAVIS WILLIAM WOODS- HILL Dec. 23, 1952 w.WOODS-HILL ETAL 2 ELECTRONIC DIVIDER Original Filed March 3, 1950 8Sheets-Sheet 2 1 N V EN TORS DAVID DSVISSH LL W M O D I 4a ILLIA 'zifzam ATTORNEY Dec. 23, 1952 w. WOODS-HILL ET AL 2,523,171

ELECTRONIC DIVIDER Original Filed March 3, 1950 s Sheet-Sheet sINVENTORS DAVID T. DAVIS WILLIAM WOODS HILLS ATTORNEY Dec. 23, 1952 w.WOODS-HILL ETAL ELECTRONIC DIVIDER Original Filed March 3, 1950 8Sheets-Sheet 4 U4 INVENTORS DAVID T. DAVIS F 5 WILJLIAM WOODS'HILL IATTORNEY Dec. 23, 19552 w. WOODS-HILL ETAL 2,623,171

ELECTRONIC DIVIDER Original Filed March 3, 1950 8 Sheets-Sheet 5W-ILLIAM WOODS-HILL QZQZM ATTORNEY Dec. 23 1952 w. WOODS-HILL ET ALELECTRONIC DIVIDER 8 Sheets-Sheet 6 Original Filed March 3, 1950 QN Q SI 9 Q S E N :Qomwmn INVENTORS DAVID T. DAVIS WILLIAM WOODS- HILL mm .s IQ I Q $5 gmmsg zyg ATTORNEY Dec. 23, 1952 w. WOODS-HILL ETAL ELECTRONICDIVIDER 8 Sheets-Sheet '7 Original Filed March 3, 1950 3 2 S t 2 Q-iumwL.

mw-wnwmw S $5 3%9 Ex m m mi 2 mm mm mv .& was 5 mmwfim a s5 3 $53INVENTORS DAVID T. DAVS WILLIAM WOODS HILL ATTORNEY Dec. 23, 1952 w.WOODS-HILL ETAL 2,623,171

ELECTRONIC DIVIDER Original Filed March 5, 1950 8 Sheets-Sheet 8 &2 LL u60 I I M59 131% 132 190 178 4z INVENTORS 1 DAVID T. DAVIS WlLLIAMWOODS-HILL ATTO ENF Patented Dec. 23, 1952 UNITED STATES PATENT OFF2,5233% ICE 2,623,171 ELECTRONIC DIVIDER William Woods-Hill, Letchworth,and David Thomas Davis, Wandsworth Common, London, England, assignors toInternational Business Machines Corporation, New York, N. Y., a cor-'po'rat'ion of New York Original application March 3, 1959, Serial No.

147,442. Divided and this application Decemher 27, 1950, Serial No.202,918.

Britain March 24, 1949 v 6 Claims. (01. 250-427) The present inventionrelates to an electronic dividing device and more particularly to anovel emitter employed as part of a device'utilizing the principle ofduplation and is a division of applicants copending application SerialNo. 147,442 filed March 3, 1950. v 7

It is possible to express a number a: in terms of any other number asthe sum of a series of terms of the general form.

x'=a2y+a2 y+a2 y+a2 y+a2 y+ a2 y-1-a2 y where each a may have the value1 or 0. v

This series will contain a finite number of terms if the quotient of :10divided by y is commensurable and an infinite number of terms if thequotient is incommensurable. However, the series converges comparativelyrapidly, so that it is possible to obtain any required degree ofaccuracy by considering a reasonable number of terms of the series.

The above expression may be re-arranged in the form:

Thus, the quotient of is divided by y is obtained. The value of thecoefficient a for each term may be determined by subtracting each term012% etc. from the value of m, or its remainders, commencing with thehighest value term. If the remainder or sub-remainder is positive, a is1, if negative, a is 0. For example, it may be required to find thequotient of 123 divided by 7. The term 2 .7 has the value 224 which isgreater than 123 while 2 has a value of 112 which is less than 123 sothat no term with a coefficient greater than 2* can appear in theseries. The calculation of the quotient may be tabulated as follows:

since the quotient of 12a divided by 'z' is 17.571.

In Great 2 correct to three decimal places as obtained by directdivision, the value obtained by taking terms with coefiicients from '2to 2" in the series turns out to be correct to two decimal places.Greater accuracy would be obtained by extending the number of termsconsidered. I

An object of the invention is to provide an emitter or commutator forsuch an electronic dividing device comprising a chain of electronictriggers operable in seriation and means continuous- 1y interrupting theseriation operation at an intermediate point in the chain and initiatinga new cycle of operation.

According to the invention, an electronic dividing machine includingtube counters for registering a divisor (DR), a dividend (DD) and aquotient (Q) and a novel tube pulse emitter are employed along withmeans to double repeatedly the said registered divisor value until it isnumerically greater than the greatest dividend value which can beregistered, means to halve repeatedly thereafter the s'aid repeatedlydoubled divisor value, means to effect transfer of each repeatedlyhalved divisor value to the dividend counter to effect subtraction ofthe divisor value from the value registered in the said counter, and ifthe said subtraction will result in a positive remain der, employingmeans for forming and summing in the quotient counter a plurality ofterms of the binary series, the said sum being the quotient value. I

In the preferred form of the invention, the electronic dividing machineincludes a novel pulse emitter in conjunction with a divisor counter,the value registered in which may be either halved or doubled, adividend counter, and a quotient counter, the value registered in whichmay be doubled, and means for comparing the values standing in thedivisor and dividend counter. The divisor value is first doubledsuccessively until it is greater numerically than the dividend. Thedivisor is then halved successively, and at each halving operation, thevalue is compared with the dividend value, and if it is less, it issubtracted from the dividend value. Each time a subtraction is effected,1 is entered in the quotient counter, and each time the divisor value ishalved, the quotient value is doubled.

Throughout the specification the term tube will be used to indicatethermionic tubes of the high vacuum type.

Other objects of the invention will be pointed out in the followingdescription and claims and illustrated in the accompanying drawings,which disclose, by way of examples, the principle of the invention andthe best mode, which has been contemplated, of applying that principle.

The invention will now be described, by way of example, with referenceto the accompanying drawings, in which:

Figures 1 and 1a, with Id at the right comprise a circuit diagram inblock form of the complete dividing machine.

Figure 2 is a circuit diagram of the cycle counter 8 of Figure 1a and ofelement 3I of Figure 1a.

Figures 3 and 3a, with 3a at the right, comprise a composite circuitdiagram showing one denomination of the divisor counter 2 of Figure 1,one denomination of the dividend counter I of Figure 1 and the relatedparts of the comparison circuit 4 of Figure 1.

Figures 4 and 4a form a timing diagram in which the positive or negativenature of the pulse is ignored to sharpen the time comparisons.

Figure 5 is a circuit diagram showing one of the transfer tube circuits6 of Figure 1a.

Figure 6 is a circuit diagram of the three stages I40, MI, and I42 ofFigure 1.

Figure 7 is a circuit diagram of any one of the cathode follower stageseach generally indicated as 63 in Figure 1 and Figure 8 is a circuitdiagram of any one of the amplifier stages generally indicated at 28 inFigure 1.

In our copending application Serial No. 147,441 filed March 3, 1950there is disclosed an electronic multiplying machine employing theprinciple of halving and doubling. The present invention employs certaincircuits described briefly herein which are generally similar to thosedescribed in said application, to which reference may be had for a moredetailed description of such circuits.

The term trigger stage or simply trigger will be used herein to denote acircuit well known in the art, comprising two tubes so cross-coupledthat the circuit has two mutually exclusive stable states. In thedrawings, unless otherwise stated, the left hand tube of each trigger isassumed to be conductive and the right hand tube to be nonconductivewhen the trigger is off. When on, the conductive conditions of therespective tubes are reversed.

The term gate tube or simply gate will be used to denote amulti-electrode tube or its equivalent so connected that a voltagechange applied to one control electrode may be prevented from affectingan output electrode by the application of a voltage to a second controlelectrode. An example of such a gate is a pentode in which a voltageimpulse is applied to the control grid and in which the voltage of thesuppressor grid determines whether or not a corresponding voltageimpulse appears at the anode.

GENERAL Figures 1 and 1a comprise a block diagram of an all electronicdividing device constructed according to the invention and designed todivide a three digit dividend by a three digit divisor to give a sixdigit quotient to three decimal places.

The dividend counter I (Figure 1) comprises six decimal denominations.The dividend value is entered with the units value in the fourthdenomination (counting from the right) of the counter, the tens in thefifth denomination, and the hundreds in the sixth or extreme leftdenomination. The divisor counter 2 is also of six denominations and thedivisor value is entered in the usual manner, that is, with the units inthe extreme right hand denomination of the counter.

The divisor counter 2 is provided with an overflow indicator 3 which isoperated when the value istanding in the counter exceeds 51 QnQminaons.

Corresponding denominations of the divisor and dividend counters areconnected to groups of comparing units 4, which are connected in chainfashion within a group. This comparer indicates when the divisor valueis greater than the dividend value and therefore cannot be subtractedfrom it to leave a positive remainder.

The quotient counter 5 likewise consists of six denominations. Theoperation is such that the first three denominations on the right recordthe decimal part of the quotient and the remaining denominations recordthe whole number part of the quotient. Whenever the divisor value isentered into the dividend counter I, through the transfer valves 6, anentry of one is made into the quotient counter by a pulse on the line 9.

The pulse emitter which controls the operation of the divider comprisestwenty successively numbered units, generally indicated as 1. Associatedwith each unit I is a pair of gates Ill. The operation of these gates iscontrolled by a switch control unit I3, via lines II and I2. When theswitch control unit is in one stable state, line II renders itsassociated gates I0 operative and when in the other stable state, lineI2 renders its associated gates III operative. For convenience ofreference, the gates I 0 connected to line II will be designated bysuflix A added to a sequence designating number so that gate III(5A) isthat gate III of the fifth emitter unit connected to line II. The gatesI0 connected to line I2 will be designated by the suflix B.

PULSE GENERATOR AND START UNITS A multivibrator and trigger unit isindicated as I4 in Figure 1, and a start unit by I5. These units arelike those in the multiplier described in our above cited co-pendingapplication, to which reference may be had for a detailed description.

Generally unit I4 comprises a free running multivibrator, the outputfrom which is applied to a single trigger stage as in said copendingapplication. From each anode of the trigger stage, the resulting squarewave is applied through a differ-' entiating circuit to the grids of twotriodes of the unit I4 which are normally biased below cut off, so thatnegative pulses appear at the triode anodes Which are applied to linesI6 and I! as indicated in reverse phase in Figure 4. Since the pulsesfrom one triode are derived from one-half of the square wave, and thepulses from the second triode from the other half of the square wave,the pulses occur alternately on lines I6 and II. A series of positivepulses is also supplied by unit I 4 via line I8 to the start unit I5.

When the start unit is brought into operation by any well known manneras for example by the closing of a key or relay contact, the positivepulses from line I8 are fed through a pentode gate tube to a triggerstage as in said co-pending application which is thereby switched to the"on state. The output pulse from this trigger stage is applied to asecond trigger stage, causing this stage to switch on. The resultingnegative pulse is applied via line I8a to the first stage 1(1) of thepulse emitter to be described presently. The fact that the secondtrigger stage of unit I5 is in the on state causes the suppressor gridof a pentode gate tube as in said copending application to be broughtfrom below cut off to cathode potential. Line 20 is connected to thecontrol, grid of this pentode, sothat a positive pulse on this line 20will, under these conditions, produce a negative pulse, at the anode,which will also go via line I9 to the unit 1(1) to initiate any furtheroperations of the emitter, as described later. A negative "pulseproduced on line 2i as described later will switch the second triggerstage of unit I5 off, thereby reducin the suppressor grid potential ofits gate tube and preventing the production of further pulses on line I9to thus prevent further operation of the emitter, at the end ofdividing.

PULSE EMITTER This consists of the units 1(1) to H120) and theassociated gates Ii]. The construction and functioning of this unitisthe same as that of the emitter described in our copending application147,441 except for the differences noted herein.

Each of the units I comprises a trigger stage from one anode of which acapacitative connection is made to the control grid of the associatedgate or gates 19. The suppressor grids of the respective gates areconnected to line II or to line I2. All the trigger stages of the units7 are normally cit.

When a negative pulse is applied to unit 7(1) via line Ifia to initiatea dividin operation as described above, unit 1(1) is switched on. Thenext pulse produced on .line I7 after this time by the MV unit I4,causes unit 1(1) to switch off again. This switching off produces .anegative pulse, which, via line .22, switches unit 1(2) on, and alsoproduces apositive pulse, which, applied to the control grid of thegates Iil(1A) and IIKIB) produces a negative pulse at one or the otherof the anodes determined by the diiierent potentials of the lines II andI2. If line I I is the one at approximately ground potential gatesIIJ(1A), Ill (2A) etc. will produce negative pulses.

Unit 1(2) will be switched "off by the next pulse produced on line It bythe MV unit I4 and in going oii will switch on unit 1(3). In thismanner, the separate units I will be switched on then ofi, progressivelyalong the chain after initiation of the dividing operation.

It is to be noted that there is a connection from. the gate IB(12A) to afurther gate 24 (Fig. 1). When unit 7(12) switches off, the gate I0(12A)will pass a negative pulse to gate 24, which will also be operative,since its suppressor grid is connected to line I I, so that a positivepulse will thus be sent via line 26 to the start unit I5 and thence as anegative pulse via line it to unit 1(1) to switch it on and commenceanother cycle of pulse emitter operation.

It is also to be noted that emitter unit l( 12) is connected to emitterunit 1(13) only via line 2% and a gate tube 23 which has its suppressorgrid connected to line I2. Since line I2 is at this time considerablynegative with respect to ground, gate 23 is inoperative and no pulse istransmitted from the anode of 23 via line 25 to switch emitter unit1(13) on, so that units 1(13) to H203 are not operated, at this time.The line 26 is connected to the opposite anode to that to which thelines 22 are connected, to provide a pulse of the correct polarity.

When, however, the switch control unit I 3 is in the other stable state,line IE will at that time be near ground potential so that the B gatetubes will be operative, together with tube 23, while gate IWlZA) willbe inoperative. Thus, under these conditions the pulse from unit 1(12)will switch on emitter unit H13) and the switching will proceedsuccessively along the entire chain to unit 1(20) which in switching offwill via 26(103) produce a pulse which, via line 21, amplifier 28, gatetube 24, line 20 and start unit I5, will switch "on unit 7(1) to commemeanew emitter cycle. Thus when the switch control unit .I 3 is in onestate, the emitter cycle isirom unit 1(1) to unit 1(12) and back to 1(1)again, and when in the other state from unit 1(1) to unit H20) and backto 1(1).

CYCLE CONTROL The number of cycles performed by the pulse emitter isdetermined by the overflow indicator 3 and the cycle counter 8 actingtogether. The switch control unit I3 consists of a trigger stage similarto the half cycle control unit described in our above cited copendingapplication. In the normal off state of the trigger stage of unit I3,the line I I is held at approximately ground potential, and the line I2negative with respect to ground, so that the gate tubes IeA connected toline H are operative.

At the very beginning of the dividing operation, the emitter cycles fromunit 1(1) to unit N12). The pulses from the related gate cause the-value registered in the divisor counter to be successively doubled, onesuch doubling operation taking place for each cycle of the emitter, aswill be described in more detail later. After a number of cyclesrequired for the successively doubled "DR value to overflow its storagewhich of course is dependent upon the original value of the divisor, theoverflow indicator 3 is flipped. This indicator consists of a triggerstage similar to those employed in the divisor counter, and it may infact be considered as the first stage of a seventh denomination of thiscounter. However, a line 29 is connected in a well known manner to apotentiometer extending from the left hand anode of this trigger stageto a negative bias line so that when this overflow switches on, thepotential of line 29 is made less negative. This conditions gate 58 sothat a plus pulse from unit I0(1 2A) via 2 3 and over line 24a renders58 operative. Thus the positive pulse applied to gate 58 from line 24ais inverted to a negative pulse, which is applied to the switch controlunit trigger stage I3 via line I as to switch it on. With switch unit Iton, and via the pulse transmitted via 24 and line 28 to the start unitI5, the emitter starts its second or long cycle of operation, in whichall the units 1(1) to R20) are used and the gate valves IEB areoperative.

During the doubling of the DR value which is called the first part ofthe division operation, for each short cycle of emitter operation, apositive pulse is transmitted via line so and ampli fier valve 28 to thecycle counter 8. This counter is adapted to perform addition orsubtraction, and at this time is conditioned for adding. Thus the totalnumber of cycles during the first part of the operation is registeredpositively in the counter.

When the switch control unit I3 goes on, a negative pulse is transmittedvia line 32 to the trigger stage 3| (shown as V 35 in Fig. 2), whichthereupon switches on. This has the effect of altering the potentials ofthe lines 33 and as, which thus conditions counter 8 for subtraction asdescribed presently. Thus the pulses which are thereafter transmitted tothe cycle counter 8 via line 30 are subtracted from the value alreadyregistered. During this time, the DR value is halved and this is calledthe second part of the division operation. When the counter passesthrough zero, indicating that the numbers of cycles performed in bothparts of the operation are equal, a negative pulse is transmitted via 7line 2| to the start unit l5. As stated above, this blocks thetransmission of pulses via line 23 to line It? and thus terminatesemitter operation.

CYCLE COUNTER The cycle counter generally indicated as 8 in Figure 1 isshown in detail in Figure 2. It comprises five trigger stages V4|] toV44, which form a straight binary counter counting to 32. Each triggerstage may comprise a twin triode valve such as a type GSN'Z.

The trigger stage V45 of Fig. 2 is indicated generally as 3| in Figure land controls the relative potentials of the lines 33 and 34. Resistors35, 31, 38 and 39, 43, 4|, form two potentiometers between the H. T.line 43 and the negative supply line 42. As stated above generally forall triggers in the normal or ofi state, the left hand valve of triggerV45 is conducting and the right hand valve non-conducting so that thejunction point of resistors 31 and 33, and hence line 33, isconsiderably negative with respect to the ground potential line 44. Thesuppressor grids of pentodes V41, V48, V50, V52 and V55, connected toline 33, will thus be held below cut-off and any pulses applied to theircontrol grids will not appear at their anodes. On the other hand, thejunction point of resistors 33 and ll, and hence line 34 is atapproximately the potential of line 44. However, when trigger stage V45flips on, the potentials of lines 33 and 35 relative to line 44, will bereversed. A more detailed description of a trigger stage similar to V35will be found in the above cited copending application.

Each of the trigger stages V4| to V44 has two pentodes associated withit serving as gates. Thus trigger stage V44, which is the first stage ofthe counter, has associated with it the gate pentodes V54 and V55. Thecontrol grids of the gates are connected to the negative bias supplyline 50 through individual resistors 45. The screen grids are commonedand connected to the H. T. line 43 through a resistor 41. The anodes arecommoned and connected through a resistor I 48 to the H. T. line.

The left hand anode of trigger V44 is connected via condenser 49 to thecontrol grid of gate V54 and its right hand anode is similarly connectedvia condenser 48 to V55. positive pulse fed via line 30 from emitterunit '|(ll) (Figure 1) to amplifier 28 is inverted to a negative pulseand applied via line 35 (Figure 2) to the grids of trigger V44 (Figure2) through the condensers 5|, causing V44 to switch on. The right-handhalf of V44 then becomes conducting so that a negative pulse is appliedvia condenser 48 to the control grid of V55 which is ineifective, sincethe grid is already below out off due to the connection to the bias line5|). A positive pulse is applied via condenser 49 to the control grid ofV54 but cannot produce a pulse at the anode since the suppressor grid isheld below cut ofi by line 33.

A second pulse on line 35 switches V44 01f, which produces a positivepulse at the grid of V55 that appears as a negative pulse at the anodeand is transmitted via line 52 and condensers 5| to the grids of V43 toswitch this stage on.

On the fourth pulse, a positive pulse will again be transmitted to V55,the negative pulse from the anode of which will switch V43 off. Thiswill cause a positive pulse at the right hand anode of V43, which, viacondenser 48, will be applied to V53. The resulting negative pulse willThe first then switch on" V42. The remaining stages operate in similarmanner, so that it will be appreciated that the trigger stages V44 toV40 will operate as an adding counter operating in the binary system.

As already explained, when the divisor counter overflows and flipsswitch control trigger |3 so that a negative pulse is produced on line32 (Figures 1 and 2), which switches V (3| of Figure 1) to the on stateso that the potentials of lines 33 and 34 are changed over renderingtubes V49, V5l, V53 and V inoperative by the suppressor grid bias, thenpentodes V41, V48, V50,

V52, and V54 are now rendered inoperative.

These latter pentodes on receipt of a positive pulse from theirassociated counter trigger stage will transmit a negative pulse to causeswitching of the next higher counter trigger stage. However, since theircontrol grids are connected through condensers 49 to the left hand anodeof the related trigger stages, they will receive a positive pulse whenthe trigger stage goes on, whereas the other set of gates received apositive pulse when the trigger stages switched off. This change has theeffect of causing further pulses on line 35 to effect subtraction fromthe value already registered in the counter.

The process of subtraction may be illustrated by a table showing thestates of the various trigger stages, the on state of a trigger beingindicated by X and the off state by It will be assumed by way ofexample, that twentyone pulses were entered into the counter beforetrigger stage V45 was switched over to condition the counter forsubtraction.

TABLE I After 1st pulse After 2nd pulse. After 3rd pulse After 4thpulse- After 5th pulse. After 6th pulse. After 7th pulse.

NMMIIIIII MNNIIHNN [NMIINNII alwlalala After 19th pulse After 20th pulseAfter 21st pulse. After 22nd pulse ..l

Nil]

Mill

MINI

are

From the table, it is apparent that any trigger stage which switches on,causes switching of the next higher trigger stage. For example, thesixth pulse on line 35 switches V44 on, which, through V54, switches V43on, which, through V52, switches V42 on, which, through V50, switchesV4| on, which, through V48, switches V43 off.

The twenty-second pulse, as shown, causes all the trigger stages toswitch on. This results in a positive pulse being transmitted viacondenser 53 to the control grid of gate valve V41, so that a negativepulse is produced at the anode and transmitted via condenser 55 and line2| to the start unit |5 (Figure 1) to bring the op eration to an end.

. Since it is necessary that the number'of cycles during the first andsecond parts of the dividing operation should be equal, in order to getthis negative output pulse to stop the emitter an extra pulse must befed to the counter during the second part of the dividing operation whensubtraction occurs. This is effected by the trigger stage 54 (Figure 1).This trigger stage is similar to those employed in the counter, such asVM for example,- except that no: connection is made-tothejunctionlofthe'condensers I. Instead, line 32 connected via line 53and a condenser toone grid, and line 21 isconnected via a condenser tothe other grid. A. connection is also made from the left handanodevia'a-condenser and line 51 to linev 3 5. Thistrigger stage 54 is normallyinthe ofi state,- but will be switched. on by the pulse on; lines 32 and5% that switches on unit 3i. -At the end ofthe first long. emittercycle, the 'negative pulse on line 21 from emitter unit H2 0 willswitchon trigger stage 54. This will result in a negative pulse beingtransmitted-by line 51 to the cycle counter 8, so thatan additional 1 issubtracted from the value standing. iitthe counter-J The pulses on line21 are only efiective to switcutriga ger stage- 54 from on "'to oft/sothat only'a single pulse willbeproduced during a complete dividingoperation.

It-will be noted that-in Figure 2, the-left. hand grids ofthevarioustrigger'sta'ge's are connected through resistors- 62 to abi as'line'iill. Thenegative potentialofthisline may be redu'ce'd toforciblyreset all. the trigger stages o'fi be'fore the beginningof adiyi'dihgioperation. This method of resetting. is usedgenerally where itis necessary for a. trigger stage to 'be' re'set at theendofthedividing, operation. I

The righthandgrids of." the trigger 'stag'es' are connected-to the biasline 59', through resistors ti, which is ata fixed negative"potential;

DIVIDEND-COUNTER A detailed" circuit diagrambf one denomination of thedividend counter, indicated generally as I in Figure 1,..is'shown'in't'he upper portions of Figures 3 and 3d'i Thiscomprises the tubes Vito VIS; V51 and V53; Also-shown in Figures 3 and 3a (in' tlie'lowerpo'rtion) is one denomination of the divisor counter comprisingtubes V2 I to V38 and V59, and'irr'the center'portion of Figures 3-and"3a'thecompai ing circuit pentodes VI! to VZUrelatedto a singledenomi nation.

Referring to the dividend denomination the trigger stages Vlii' to Vft3'as indicated by the numbers #1,, #2, #4,, #ureprese'nt these values; Thetrigger stage Vl2 (Fig; 3')" is labeled C, to indicate that it istheparry trigger stage:

The dividend counter" is operable as both an adding and subtractingcounter'an'd operates substantially like'the' cycle counter 8; Eachdenomination operates" as a binary counter in- 1 the scale of IS andis'then' corrected to read-in the decimal scale. However, unlike thecycle counter, the values are not registered by applying a succession ofpulses to the'lowest value trig ger and operating in cascade but insteadby directly setting the appropriate triggers individually in eachdenomination;- This might be-termed a sidewise operation: in contrast tothe serially spilling over cascade operation of cycle" counter 8.

During the actual divldingbperation, the dividend counter alwayssubtracts: so that the gates V4, V6, V8 and V), which permit the counterto add, are rendered 'noperauveas described seen that the anodes of thetrigger, like those in the cycle counter 8, are respectively connectedthrough condensers H15" and [at to the control grids of pentodes V9 andVii]. The suppressor grid of V9 isconnected via resistor It? to line 9?whose potential is controlled like that of line 34 in Figure 2. If thisline is at approximately the same potential as line 54, which-is thecondition for subtracting, then whenvls switches on, a positive pulsewill be transmitted via condenser I to thecontrol grid of pentode Vii,which is connected via a'resistort'o the bias line 99, and will producea negative" pulse at the anode, which, via condenser its} and thecondensers 5|, will be applied to the control grids of the #2 trigger2H5 toswitch it on. Conversely, if line 9? is negativeand'line 9B is atthe' potential of line M, which is the" condition for adding, thenpentode Vlfiwill be operative and #2 stage VIE" will be switched fon,when #1 stage Vl't is switched off. Thus the operation of this Stage'ViEis similar to that of a stage of the cycle counter under both additionand subtraction;

After a subtraction has been performed; the value'register'ed in adenomination" of the dividend'counter maybe upto' I5 and furthermore,

any carry which has been registered by the switching on of the carrytrigger stage represents a carryof lfi'andnot of 10. It is necessarytocorrect thesevalues to ten. Firstly, six'is added into eachdenomination. If the value initially registered was less than six, thena carry will'oc'cur, setting stage Vl2' on. To effect correction afurthervalue of tenis added in any denomination in which'the'carrytrigger stage is set; Thus a total of sixteen will have been added insuch a'denomination and the original value registered will be obtained;If, however, thevalue initially was six'or-more, then no carrywilloc'cur' and theva'lue registered will bethe correct decimal value;

Prior to these corrections mentioned above, the counter is conditionedfor subtraction by line 98 being made negative and line 91 set at thesame voltage as'line 44; When #8 trigger stage V13 switches on, a;negative pulse is transmitted via condenser I65 to thecontrol'gridofvii;this tube is normally conductive, with lines! at the same voltage asline H, as described in detail below, so that a positive'pulse' nowappears at the anode, which pulseis inverted and transmitted by V51 andcondenser ll'O' and condensers 51, to causecarry stage Vl2t0 switch on.As a resuit, the anode potential of'the left hand half of VI? rises andthejunction of resistors [I2 and l I3is brought up from a negativepotential to the potential of line 44. Thus, when a positive pulse (seeCarry'Pulse Divid. Fig. 4a), derived from emitter unit 7(12) via gateIE3(12B) and amplifier 28 (Figure 1) appears on line 88, a negativepulse is produced at the'anode of VI l, the control grid of this'pentode now being held above cut-off, and istransmittedvia'condenser H8and line lflfle to the #ltrigger in the next higher denomination. (Thecarry input from the next lower denomination is labeled I00 in Figure3a). The carry to the next denomination having been made, the carrytrigger VIZ is reset (see Reset Carry Trigger Divid; Fig. 4a) by anegative pulse on line 89. This negative pulse can only reset thetrigger off and not switch if on, since the connection is madeasymetrically with respect to"the condensers 5|, directly to the righthand control grid vi'a condenser I I9.

Having'cle'a'red" thecarry; and" reset the carry trigger, the correctivevalue 6 must be added, as stated above, in each denomination, and thisis effected by adding 2 and then 4. A negative pulse from emitter 1(14)via gate I9(14B), cathode follower 63 and line 90 (Figure l), is appliedto the #2 trigger VI (Figure 3 a) via condensers I29 and 5| to cause itto switch over and thus add two to the value registered in the counter(see Add 2 Quot. 8a Divid. Fig. 4a). In a similar manner, a pulsederived from emitter unit 1(15) is applied to #4 trigger VI4 viacondenser I2I and line 9i to cause the addition" of four (see Add 4Quot. 8: Divid. Fig. 4a)

As already noted, if the initial value registered was less than six,then the carry trigger VI2 will have been set on after the addition ofsix. If VI2 is on, then the junction point of the resistors H2 and H3forming part of the potentiometer II I, H2, H3, will be positive withrespect to line 44. Since this point is connected to the control gridsof the pentodes VI and V2, these pentodes will be rendered operative.Thus with trigger stage VI2 on, when a positive pulse is applied to thesuppressor grid of V2 from emitter unit 1(17), gate I9(17B), amplifier28, line IIlI (Figure 1) and condenser I24 to add -2, a negative pulsewill appear at the anode of V2, and be transmitted via condenser I25 andcondensers 5I to the grids of the #2 trigger VI5 to effect switching andthus add two to the count (see Add 2 Quot. & Divid., at 17 time Fig. 4a)In similar manner, a positive pulse on line 93 from IIl(18B) will effectthe addition of eight (see Add 8 Quot. 8: Divid., Fig. 4a).

The connections between #8 stage VI3 and gates V3 and V4 differ from theother stages because the interposition of carry blocking tube V5! causesan additional change of polarity of the pulse. This necessitatesconnecting V3 to the right hand anode of #8 trigger VI3 while V4 isconnected to the left hand anode of VI3. Furthermore, the grid resistorsI21 and I28 are returned to line 44, instead of to the bias line 99, sothat these values are at zero bias and therefore are operated bynegative pulses only. The gate V51 prevents switching on of the carrytrigger VI2 during the period when the ten corrective value is beingadded.

The line 92 connected to the suppressor grid of V51 is normally at thepotential of line 44, thus allowing V5! to pass a pulse from V3 or V4 toswitch the carry trigger on. However, prior to the addition of ten, (seeCarry Suppression, Fig. 4a) line 92 is made negative so that any pulseon the control grid of V5! is ineffective to till 12 equivalent to H5and H6, so that when trigger I22 is switched on by the pulse from gateIIl(16B) (Figure 1), line 92 is made negative and when I22 is switched01f by the pulse from gate lIl(19B), line 92 is returned toapproximately ground potential.

If any of the dividend denominations is at zero and then receives acarry, (all prior to correction of the counter indication) acarry-on-carry or long carry will be produced. This arises since thecounter is set for subtraction and thus if all the stages are off, onepulse will cause the stages to turn on" in succession, as noted inconnection with Table I for subtraction with the cycle counter 8. Thetube V58 is provided to deal with this long carry. As shown in thetiming diagram Figure 4a, (Long Carry) this tube V58 is operative in theperiod during which carry takes place. If a long carry is generated,then a positive pulse will be produced at the control grid of V51, as inthe case of a normal carry. This pulse will also be applied via line I29to the control grid of V58, producing a negative pulse at the anodewhich is transmitted to line Ilifla via condenser I30. Thus, valve V58act in effect as a by-pass to the normal carry circuit of VII and VI2during the carry period. The suppressor grid of V58 is controlled fromtrigger I02 (Figure 1) via line I03. This trigger is similar to triggerI22, the line I03 being connected to the potentiometer from the lefthand anode, so that when the trigger is off, line I03 is negative withrespect to ground, and at ground potential when the trigger is on.Trigger I02 is switched on by a pulse from gate IIJ(12B) and "01? by apulse from emitter unit 1(14) produced when this unit switches on.

The divisor value is transferred to the dividend counter by a pulse onthe appropriate line or lines 96(1), 99(2), 96(4) and 96(8), (Figures 1and 3a), in each denomination. That is, if the value seven were to betransferred, then a single pulse would be transmitted on each of thelines 96(1), 96(2% and 96(4) these pulses being in the order 8, 4, 2, i.

In order to illustrate the various steps in the subtraction of thedivisor from the dividend, the subtraction of 288 from 345 is shown byway of example in Table II. In this Table II, X represents that atrigger is on.

It will be noted that reference has been made above to adding six andten. The expression adding is used here since the subtraction, whichactually takes place, is due to the mode of operation of the counteritself and not to the form in which the entry is made.

TABLE II IINNMM MMMMIN IMNMNII MNNNNNI INNNMIN NI 1 l I ll llill llllNNNNN] lllll MNNNM NIIIIII Dividend 345.

Divlsor 286.

Transfer pulse 8 to dividend. Transfer pulse 4 to dividend. Transferpulse 2 to dividend. Transfer pulse 1 to dividend. Carry in dividend andreset carry.

stage C Add 2 in dividend.

Add 4 in dividend.

Add 2 only if 0 is on." Add 8 only If C is on." Reset carry.

Value registered.

Illil INNIIII NNNNN NNHIII] llll NNNINNN Illll NNNIINI NMHMN NNNNNINproduce a pulse at the anode. Line 92 is connected to a trigger I22(Figure 1) similar to the carry trigger VI2 (Figure 3) and line 92 iscon- From Table II it will be seen that during the actual subtractionprocess, the mode of operation is very similar to that of the cyclecounter 8 with nected to the junction point of the resistors the value,however, being entered by selective direct pulsing of the individualtrigger stages (or sidewise operation) instead of cascadeoperation as incounter 8 by entry of the appropriate number of pulses into the lowestvalue trigger stage.

The dividend value may be initially entered into the counter in anydesired manner, as, for example, by pulsing the appropriate lines 56.

DIVISOR. COUNTER This counter is generally indicated by Zin Figure 1,and is shown in detail in the lower part of Figure 3, and comprises thetubes V2! to V39 and V59.

The counter may be conditioned selectively either for successivelydoubling the value registered therein or for successively halving thisvalue. It thus effectively combines the features of the multiplier andmultiplicand counters, as described in our above cited copendingapplication, to which reference may be had for a more detaileddescription of the steps involved in these two functions.

Considering, for example, the #2 trigger stage V25 (Figure 3a aconnection is made via the condenser 135 to the control grids of the twogates V31. and V35 in parallel. The suppressor grid of Vt l is connectedthrough a resistor I31 to the line I31, (Figure 1 and Figure 6). Whenthe trigger Vtii (Fig. 6) of element let (Fig. 1) is off, the line |3I(Figures 6, 3a and Figure 3) is at approximately ground potential, andaccordingly V34 (Fig. 3a) and the similarly connected pentodes V23, V29,V30, V32 (Fig. 3) and V36 (Fig. 3a) will be operative. When #2 triggerV25 switches cit a positive pulse will be transmitted to the controlgrid of pentode V34 via condenser llii, and will appear as a negativepulse at the anode of V34, which, via the condensers I38 and 51, will beapplied to the grids of #4 trigger V24 to switchit over. Thus the abovementioned gates, when V8.8 of Fig. 6 is oif, allow each trigger when itswitches from on to ofi to switch the next higher trigger, to thusproduce doubling.

When the trigger V60 is on, the line I 32 (Figs. 6, 3a and 3) will be atapproximately ground potential and the gates V31, V33, V35, V31, V38 andV39 will be operative. In this case,when trigger V25switches offja pulsewill be transmitted via the pentode V35 and thecondensers I39 and toswitch over the #1 trigger V26, that is, when each of the triggersswitches off, it now switches over the next lower trigger stage, to thusproduce halving.

As already noted, during the first part of the division operation, thevalue in the divisor counter is doubled, so that pentodes V28, V29, V39,V32, V34 and V36 will be operative. The lines 65, 65, er and 68 areconnected via condensers to the right hand grids of the triggers V23,V24, V25 and V2ii, so that a negative pulse on these lines will causethe related trigger to switchfoff, if itis in the on condition that iswith the right hand valve conducting. At the very beginning of a shortemitter cycle, a negative pulse from gate lil(lA) is transmitted via thecathodefollower stage 63 and line 65 to all the #8 triggers of thedivisor. If any of these triggers are on, then they will be switched offand the pulse produced at the. left hand anode will, via the relatedgates- Vilil (Fig. 3) and pentodes V59, switch on the carry up triggerV22 in much the same way as the valves V4 and V51 in the dividendcounter. A negative pulse from |(l(2A) is then similarly transmitted vialine 66 to all the #4 triggers. Any one of these which is on will beswitched off and through the gates V32 will switch on the #8 triggerV23. Succeeding pulses on the lines 61 via l0(3A) and 68 via l0(4A) willcause the switching of the #2 and #1 triggers. In this manner, the valueregistered in the counter is doubled. the value of the carry triggerstage being regarded as iii. In order to correct the value in eachdenomination to the scale of 10, it is now necessary to add 6 and 10.Pulseson the lines 69 and 19 add 2 and 4, respectively, (see Add 2 inDVR and Add 4 in DVR Fig. 4). Further, the pentodes V28 and V29correspond to the pentodes VI and V2 of the dividend counter and ifcarry trigger CU is not on control the addition of 10, while the pentodeV59 corresponds to the pentode V51 and when conditioned by a negativepulse on line 1! via MEGA.) and unit 16 (until HA flips 16 back)prevents the setting of the carry-trigger stage durin this addition of10 (seeCarry Suppression in DVR Fig. 4). Since the value, afterdoubling, must be even, the addition of a 1 carry cannot cause-a furthercarry, so that no equivalent to V58 is required. The entry of the carryand the resetting of the carry stage are similar to these functions inthe dividend counter but occur at different times (see Carry Pulse DVRand Reset Carry Triggers DVR, Fig. 4).

As stated above, when the trigger V69 (Fig. 6) is on, the counter isconditioned for halving, that is to say, the gates VSI, V33, V35 and V3!are operative and also pentodes V38 and V39. In order to eifect halving,the lines to 53 are again individually pulsed, but this time in thereverse order, that is, the #1 trigger is pulsed first and the #8trigger last, as described in detail later. If #1 trigger V25 is on whenit is pulsed, then it will be switched off, and through gate V31, apulse will be applied to the carry down trigger V21, which wil-ltherebybe switched on. If the #2 trigger V25 is on, then, in being switched offitwill switch on the #1 trigger V25 and similarly for the remainingtriggers. Thus, the value registered in the counter is halved, the carrydown trigger V21 being considered as representing the value .5.

In order to make a carry down, it is necessary to enter 5 in the nextlower denomination. This requires that the lower counter be conditionedfor adding in the normal way, that is,each trigger stage must set thenext higher one (see DVR Control Voltage and DVR Add Control VoltageFig. 4a). Since the initial valuehas been halved, there cannot be morethan 4 registered in any denomination, which, together with the addedcarry of 5, cannot produce a further carry. The conditioning ofthecounter for adding this carry down is effected by the trigger stageV69 being switched off again, as explained in detail later. A positivepulse derived from gate 10(5B) ampli fier 28 and line 33 (Fig. 1) (seeAdd 1 Carry Div. Fig. 4a) is applied to the suppressor grid of pentodeV39 (Figure 3a). If the CD trigger stage V21 is on, then the controlgrids of V38 and will be approximately at earth potential, so that thepositive pulse on the suppressor grid of V39 will produce'a negativepulse at the anode, which, via condenser Hi4 and line I33, is applied tothe #1 trigger in the next lower denomination to switch it over, as isalso indicated bythe line 133d.

Each of the triggers V23, V24, V25. V26 is provided with a potentiometercomprising (see V26. Fig. 3a) the left hand anode resistor I44 andresistors I65 and I46. When the trigger stage is off, the junction pointof resistors I45 and I46 will be negative, and when the trigger stage ison, the junction point will be at ground. To each of thesepotentiometers, the lines 95(8) (for V23), 95(4), 95(2) and. 95(1) (forV26) are respectively connected. These lines go to the control grids ofthe transfer pentodes labeled 6 (Figure 1) and shown as V65 in Fig. 5.Thus, when a particular trigger is on it renders the related transferpentode operative, so that when a positive pulse is applied to thesuppressor grid of the transfer pentode, a negative pulse will appear atthe anode on one of the lines 96 and thus effect entry of the value intothe dividend counter as already explained.

The divisor value may be initially entered by applying pulses to thecontrol grids of V26, V25, V24 and V23 via the required combination ofthe lines I58(1), I58(2), (Fig. 3a) I58(4) and 158(8),

(Fig. 3) in each denomination.

COMPARING CIRCUIT Since it is required that the divisor be subtractedfrom the dividend, only when a positive remainder will result, it isnecessary to compare the values of the divisor and dividend to determinewhether subtraction should take place. This comparison is effected by agroup of pentodes VI1, V18 (Fig. 3), VI9 and V20, in each denomination(Figure 3a). This circuit actually indicates if the divisor is greaterthan the dividend, so that the control circuits are arranged in such aWay that subtraction normally takes place and is only prevented fromtaking place when the appropriate indication is obtained from thecomparing circuit. Each of the pentode in the comparing circuit operatesin the same way so that only one will be described in detail.

The suppressor grid of pentode VI1 (Fig. 3) is connected through aresistor I41 to the right hand anode of the #8 trigger VI 3 in thedividend counter, and through an equal resistor I48 to the left handanode of the #8 trigger V23 in the divisor counter. The suppressor gridis also connected through a further resistor I49 to the control grid,which is connected through a resistor E50 to the negative supply lineI5I. Since the resistors I41 and I40 are connected to opposite anodes ofthe trigger stages of the dividend and divisor counters, then thesuppressor grid may assume one of three potentials, depending uponwhether the related triggers are on or ofi.

(1) If #8 trigger VI3 of DD is on" and #8 trigger V23 of DR is off, thenthe right hand tube of VI3 and the left hand tube of V23 will beconducting, so that the suppressor grid will assume a minimum potential.

(2) If both triggers are on or both off," then the suppressor grid willassume an intermediate potential, since either resistor I41 or I48 willbe connected to a higher potential anode and the other to a lowerpotential anode.

(3) If DR is greater than DD, #8 trigger V23 of DR is on and #8 triggerVI3 of DD is off and the suppressor grid of VI1 will assume its maximumpotential, since both resistors I41 and I43 will be connected to anodeswhich are at the higher potential.

The potentials of lines I5I, I54 and I53 are so adjusted relative toline 44 that in condition both the control grid and the suppressor gridof VI1 are below cut-off potential. In condition (2) the control grid isabove cut-off but the suppressor grid is below cut-off potential, andaccordingly a pulse will be produced at the screen grid, but not at theanode. In condition (3) both control grid and suppressor grid are abovecut-off potential, so that a negative pulse will appear at both theanode and the screen grid.

The anodes of all the comparing pentodes are commoned and connected tothe supply line I53 through a resistor I55. Thus, if a particular triger stage in the divisor counter is on, without the corresponding stagein the dividend counter being on, then a negative pulse will be producedin the common anode circuit and be transmitted via condenser I56 andline I51 to the subtracting control trigger 81 (Fig. 1) which isnormally set to permit subtraction but will now prevent such subtractionsince DR is greater than DD.

If the value represented by the dividend and divisor triggers #8 forexample is the same, the suppressor has an intermediate potential and apulse is produced at the screen grid. Since the pulse applied via line82 to the control grid is positive as described presently, this screengrid pulse will be negative. However, the time constant of the condenserI59 and resistor I 50 is sufficiently small for partial differentiationof the pulse to occur, thus producing at the control grid of the nextlower pentode in the chain a negative pulse coincident with the leadingedge of the screen grid pulse and a positive pulse coincident with thetrailing edge. This latter pulse will then act as the input pulse forthis lower pentode. Thus, if a number of trigger stages in the divisorand dividend counters are in the same states, a pulse will travel downthe chain of comparing pentodes, the pulse to operate each pentode beingderived from the screen grid of the next higher in the chain. Thepositive pulse to the control grid of the first comparing pentode VI1 isapplied via line 82 and amplifier 28 (Figure 1).

If the divisor is lower in value than the dividend at any particularpoint along the chain of comparing pentodes, then both grids of therelated comparing pentode will be below cut-oflf and a pulse will not bepassed on to the next lower stage. This is immaterial since the valuesrepresented below this point cannot alter the result.

The subtraction control trigger stage 81 (Figure 1a) is similar to thosealready described in which the right hand anode resistor forms part of apotentiometer and the line I60 is connected to the junction of the twolower resistors of the potentiometer. At the start of the dividingoperation this trigger stage is on so that line I60 is at a negativepotential and the suppressor grids of gates I0(8B), I0(9B), I0(10B) andI0(11B) are held below cut-oil, being connected to this line I60 insteadof line I 2. The pulse which switches switch control unit I3 on is alsotransmitted by a cathode follower 63 and line I62 to stage 81 to switchit off and thus bring the line I60 to ground potential.

A pulse on line I51, indicating that the divisor is larger than thedividend, causes this trigger stage 81 to switch on, thus disabling thegates connected to line I60 before they can initiate subtraction.Emitter unit 1(13) via gate I0(13B) supplies a pulse to reset stage 81to the off state if it has been switched on by a pulse on line I51.

TRANSFER TUBES These transfer tubes are pentodes, labeled 6 in Figure laand a detail pentode circuit is she in Figure 5.

One of these transfer pentodes (24 in all) is provided for each andevery trigger of all orders of the divisor counter. The control grid ofeach pentode for example V55 (Fig. 5) is connected to the relateddivisor trigger circuit by a line 9-5 (Figures la, 1 and 5, or 95(8),95(4), (Fig. 3) 95(2) and 95(1) (Fig. 3a) and the anode is connected tothe related dividend trigger by a condenser I64 and line 95 such as96(8) of Fig. 5. The suppressor grid of each transfer pentode isconnected to the bias line 99 (Figure 5) through resistor I66, and forthose pentodes which are connected to #8 trigger stages, a connectionthrough condenser m5 to line 551(8) permits transfer when plus isapplied to this line. Line l6l(8) is connected to line 83 via amplifier23 and a cable (Figs. 1a and 1) as described presently. Similarly line85 is connected to the suppressor grids of the transfer pentodesrelating to the #4 trigger stages, line 35 to the #2 transfer pentcdesand line 86 to the #1 transfer pentodes. For clarity of illustration,these four lines 83-85 are shown cabled as 153 with a single amplifier28 (Figures 1a and 1). The negative pulse from gate WGZB) will appear asa positive pulse at the anode of amplifier 28 and will be transmitted tothe suppressor grids of all the #8 transfer pentodes by lines it'HS) andcondenser-s I65. If the control grids of any of these pentodes are abovecut-off, due to the divisor #8 triggers being on, then a negative pulsewill be produced at the anode which, via condenser I64 and line 96(8)will be transmitted to the #8 trigger stage in the dividend counter, asalready described. Since the gates ld(8B), IMQB), [6(103), and l(1lB)are controlled by the subtraction control trigger stage 31, transferwill take place only if this stage is off with line I60 at ground E, asstated above. Since the dividend-counter is conditioned for subtraction,then the transfer will result in the divisor value being subtracted fromthe dividend value.

QUOTIENT COUNTER This counter is indicated generally as in Fig- .ure 1,and is not shown in detail since it is iden tical with the decimaldenominations of the multiplicand counter, shown in our above citedcopending application. This counter is impulsed once each cycle, inwhich subtraction occurs, to add a one therein and as described laterthe value registered therein is doubled whether such subtraction occursor not.

The entry of unit increments of the quotient value is made in thefollowing manner:

Whenever the gate (1113.) operates, that is to say, whenever asubtraction of the divisor from the dividend does take place, a negativepulse is transmitted via line 9 to the lowest value trigger stage in theunits order of thequotient counter 5. Thus the final quotient value isbuilt up by enteringl every time subtraction takes place, and .furtherby doubling the value registered in the quotient counter foreachcomplete emitter cycle taking place during thesecond half of theoperation as described later.

.ATJXILJARY CONTROL CIRCUITS In Figure 6 .a detail circuit diagram isshown of the trigger stage '1 to indicated'as V6 0 in Figure 6 and thecathode follower stages "I41 and 142 indicated as V61 and V62,respectively, in Figure 6 which control whether the divisor counter isconditioned fcrihaivins'oruoubhns.

The left hand grid of the trigger stage V60 is connected through theresistor I99 to the reset bias line 50, so that this trigger stage isinitially set in the off state. The junction point of the resistors H2and I73 forming part of the potentiometers Ill, I12 and H3 willtherefore be at a lower potential than the junction point of theresistors H5 and H5, which form part of the potentiometers I14, I75,I16. Thus the grid of the cathode follower stage V6i will be lower inpotential than the grid of the cathode follower stage V62 so that therewill be a smaller anode current through vs: than through V62 with acorrespondingly smaller voltage drop across the cathode resistor iii!than across the cathode resistor let. The line I32 will then be negativewith respect to line 13! so that the gates V38, V32, (Fig. 3) 73d and V(Figure 3a) will be operative and the gates V3l, V33, V35 and V3! willbe inoperative, that is to say, the divisor counter initially will beconditioned for doubling.

The negative pulse which switches on switch control unit It (Figure 1)will also be transmitted by line 1.68 and condenser ill (Figure 6) tothe left hand grid of V60, to switch it on. The relative potentials ofthe grids of the cathode followers V6l and V 52 will be reversed andconsequently the relative potentials of the lines it! and I32 will alsobe reversed and the divisor counter will now be conditioned for halving.

A connection is made from the right hand anode of emitter unit 7(5), viathe line I18 and condenser H9 (Fig. 6) to the right hand grid of triggerstage V of control stage It!) (Fig. 1) thus switching the trigger stageoff. Thu-s the divisor counter is conditioned at this time for doubling,i. e. adding, in which condition it can accept any carry down 5 carries,which may be produced under control of the on carry down trigger stages,which also start at this time. After this carry entry has beencompleted, a further negative pulse from gate 5007B) via lines 82 and Iand condenser I81, is applied to the left hand grid of trigger stage V69to switch it on again (see DVR /2 Control Voltage DIV Add ControlVoltage Fig. 4a) thus conditioning the divisor counter for halving,which will take place however only at the beginning of the next emittercycle.

In Figure '7 is shown a circuit diagram .of a cathode follower stage,each designated 63 in Figure 1. These stages are used purely forisolating purposes, since they provide a low impedance output of thesame polarity as the input when it is required to feed a number ofstages from a common line. The stage shown in Figure 7 correspondsspecifically to that shown in line 182 at the right side of Figure 1which controls entry of the carry in the quotient counter. A negativepulse is applied to the grid of V63 from gate 10(193) via this line I82and condenser I84. A negative pulse of slightly less amplitude willappear across the cathode load resistor E83 and be transmitted bycondenser 85 and line .64, to all the carry tubes in the quotientcounter. The low impedance output provided by the cathode follower stagegreatly assists in preventing interaction between the various stageswhich may .be connected to the common line. It may be noted that cathodefollower stages are actually used interposed in the following lines(Figure l)-'69 10, T5, and 89. These are omitted from the drawing in theinterests of clarity.

The amplifiers designated 28 in Figure 1 are employed when 'itisnecessary to convert the normal negative pulse output of the gates In to19 a positive pulse. The circuit diagram of a typical stage 28, forexample that connected in line 83 between the gate [(8B) and the #8transfer pentodes 6, is shown in Figure 8, The control grid of thepentode V64 (Figure 8) is connected to the ground potential line 44 sothat when a negative pulse is applied to the grid via this line 83 andcondenser I36, the pentode is cut off and a positive pulse appearsacross the anode load I89. This pulse is transmitted via condenser I88and line I61 (8) to the #8 transfer pentodes E (Figure 1a). Amplifiers28, not shown in Figure 1, are also interposed in the lines 12, 13, and1t.

OPERA'IIOlI DURING DIVISION The operation of the various counters in thedividing device having been explained individu ally, the functions whichoccur within the cornplete emitter cycles in both the first and secondhalves of a complete division operation will now be considered. In thisconnection, reference to Figures 4 and 411 will show the relative timingof the various functions. The functions will be set out as a series ofsteps, the numbering of the steps corresponding to the number of theemitter unit which controls the function.

In the first half of the dividing operation, the

value registered in the divisor counter is doubled once for each shortemitter cycle Step 1.A pulse is applied (see Doubling DVR, 8s, Fig. 4)to all the #8 trigger stages in the divisor counter via line 65; thusswitching off any which are on and thus switching on the correspondingcarry up trigger stages. The trigger V60 of control trigger stage I40(Figs. 1 and 6) is at this time in "off status to condition line I31relatively plus and thus condition the divisor counter for doubling.

Step 2.The #4 trigger stages (see Doubling DVR 4s, Fig. 4) of thedivisor counter are pulsed via line 66 to effect doubling of 4 into 8.

Step 3.--The #2 trigger stages (see Doubling DVR 2s, Fig. 4) aresimilarly pulsed via line 61.

Step 4.-The #1 trigger stages (see Doubling DVR ls, Fig. 4) aresimilarly pulsed via line 68.

Step 5 .-A pulse on line 69 causes 2 to be added (see Add 2 in DVR, Fig.4) as part of the corrective 6 into each denomination of the divisorcounter (Figure 1 and Figure 3a).

Step 6.-A pulse on line 10 causes 4 to be added (see Add 4 in DVR, Fig.4) into each denomination of the divisor counter, thus completing theentry of 6 which forms part of the cycle for correcting the valueregistered in the scale of 16 to a scale of 10.

Step 7.A negative pulse from gate I 0(7A) switches trigger stage 16 on,which, via line 1| (Figs. 1 and 3) cuts off the carry pentodes V59 (seeCarry Suppression in DVR, Fig. 4) in the divisor counter (Figures 1 and3).

Steps 8 and 9.A pulse on line 12 (see Add 2 in DVR at 8 time, Fig. 4)and a pulse on line 13 (see Add 8 in DVR, Fig. 4) add 2 and 8,respectively, in each denomination of the divisor counter in which thecarry trigger stage is not set. Thus a total of 16 will have been addedin such denominations and they will have been returned to theregistration which existed, prior to the addition of -6 (2 and 4,respectively) in steps 5 and 6.

Step 10.-A pulse on line 14 is transmitted to all the carry pentodes V2!in the divisor counter (see Carry Pulse DVR, Fig. 4) so that for anydenomination in which the carry trigger stage is set a carry of 1 willbe made into the next higher denomination.

Step 11.--A pulse on line 15 causes the resetting (see Reset CarryTriggers DVR, Fig. 4) of all the carry trigger stages to their offstate. A pulse from emitter unit 1(11) via line 39, the amplifier stage28 and line 35 causes the additive entry of 1 (see Pulse to CycleCounter, Fig. 4) in the cycle counter 8 (Figure l and Figure 2).

Step 12.--A pulse from gate 13(12A) via the gate 24 and line 29 (seePulse to Start Unit, Fig. 4) transmits a pulse to the start unit [5 toswitch emitter stage 1(1) on and commence a new short emitter cycle.

Further cycles of doubling of the divisor value will occur until thedivisor value exceeds six denominations, when the switching on oftrigger stage 3 (Figure 1) will cause the switching on of switch controlunit l3 as already explained. At the same time, the cycle counter 8 willbe conditioned for subtracting instead of adding by the unit 3| (V45 ofFig. 2) and trigger stage 54 also will be switched on. The stage [fill(Figure 1 and Figure 6) will also be switched on to condition thedivisor counter for halving. By the switching on of the switch controlunit 13, the gates IDA are rendered inoperative and the gates lilBoperative, so that the second half of the operation will now start.

Step 1 (second hCLZf).-A pulse from gate 18(113) via cathode followerstage 63 and line '68 is applied to all the #1 trigger stages in thedivisor counter to cause halving of this value (see Double 8s QUO. Halvels DIV., Fig. 4a) and consequent operation of the carry down triggerstage V21 (Figure 1 and Figure 3a). The same pulse, through anothercathode follower stage 63 and line 15, is applied to all the #8 triggerstages in the quotient counter to cause doubling of this value withconsequent operation of the carry trigger stage.

Step 2.A pulse from gate 18(2B) via the cathode follower stage 63 andline 61 causes halving of the #2 trigger stages (see Double 4s QUO.Halve 2s DIV., Fig. 4a) in the divisor counter and the same pulse viaanother cathode follower stage 63 and line 11 causes doubling of the #4trigger stages in the quotient counter.

Step 3.Similarly, the pulses on lines 66 and 18 cause halving of the #4trigger stages in the divisor counter and doubling of the #2 triggerstages in the quotient counter (see Double 2s QUO. Halve 4s DIV., Fig.4a).

Step 4.Pulses on lines 65 and 19 cause halving of the #8 trigger stagesin the divisor counter and doubling of the #1 trigger stages in thequotient counter (see Double ls QUO. Halves 8s DIV., Fig. 4a).

Step 5. A pulse from the gate 1(5B) via the amplifier 28 and line isapplied to the tubes V39 in the divisor counter so that if the carrydown trigger stage V21 is set, then 1 (out of 5) is added (see Add 1Carry DVR, Fig. 4a) into the next lower denomination (Figure 1 andFigure 3a). Also, a negative pulse from emitter unit 1(5) when itswitches on is applied via line I 18 and condenser I19 to the right handgrid of the trigger stage V60 of doubling and halving control stage I40(Figure 1 and Figure 6) to switch it off, thus conditioning the divisorcounted to add any 5 carries (see DVR. /2 Control Voltage, Fig. 4a)which may be entered.

Step 6.Similarly, a pulse from I0(6B) applied 21' via amplifier 28 andline 8| to the tubes V38 (Figure 3) in the divisor counter will causethe addition of 4 (see Add 4 Carry DVR, Fig. 4a) in the next lowerdenomination, thus completing the carry down of 5.

Step 7.-A pulse on line 82 from IIJ(7B) is transmitted to the firstpentode of the chain of comparing pentodes (see Comparing Pulse, Fig.4a). If the divisor value is higher than the divi dend value, then apulse will be produced on line I51 which will switch trigger stage 81(Fig. in) "on, and thus prevent subtraction taking place on this cycle(see Subtract Control,- Fig. 4d). A pulse is also transmitted via line'82 and line I80 to stage I40 to switch it on and thus condition thedivisor counter for halving once again (see DVR Control Voltage, Fig.4a).

Assuming we reach a condition in which D1; is

not'greater than DD in which condition 87 is 'fi to permit subtraction.I 7

Step 8.'-A pulse on line 83 via cable I63 and amplifier 28 and line51(8) will be transmitted to the suppressor grids of all the #8 transferpentodes 6 (Figure 1a) to cause transfer of this value to the dividendcounter in any de'non'iinations in which the #8 divisor trigger stagesare set on (see Transfer 8 DVR to DIVID., Fig. 4a).

Steps 9, 10 and 11.'-"-'-Similarl'y, pulses in succession on lines 84,85 and 86 will cause transfer of the divisor values 4 arm eachdenomination (see Fig. 4a) into the corresponding denominations of thedividend counter. Since this counter is conditioned for subtraction, thedivisor value will be subtracted from the dividend value to leave apositive remainder. A pulse from gate [M 11B) will also be transmittedvia line 9 to the lowest value trigger stage of the units order of thequotient counter (see Add 1 IN QUOT., Fig. 4a) toenter 1 therein. As inthe first half of the operation, a pulse will also be transmitted fromemitter unit 1(11) to the cycle counter (see Pulse to Cycle Counter,Fig. 4a) which has been set for subtraction by stage 3 I.

Step 12.-A pulse on line I82 will via amplifier 28 and line 88 beapplied to all the carry tubes in the dividend counter (see Carry PulseDIVID., Fig. 4a) and also will switch trigger stage I 02 on. This stagevia line I83 makes operative the tubes V58 in the dividend counter (seeLong Carry, Fig. 4a) to deal with a long Carry should this occur (Figure1 and Figure 3).

Step 13.A pulse from gate IIl(13B) is transmitted via line 89 to resetall the carry trigger stages in the dividend (see Reset Carry TriggerDIVID., Fig. 4a.) and also trigger stage 81 was switched on by a pulsefrom the transfer unit when DR is greater than DD to switch this stage"oif (see Subtract Control, Fig. 4a) and thus prepare the subtractioncontrol circuit for a subtraction operation on the next cycle.

Step 14.A pulse via CF 63 on line 90 causes a corrective -2 to beentered in all denominations of both the quotient and dividend counters(see Fig. 4a) and a negative pulse from emitter unit I (14) whenswitching on switches off trigger stage I02, thus rendering the longcarry circuit (see Long Carry, Fig. 4a.) once more inoperative.

Step 15.--A pulse via CF 63 on line 9| causes the entry of a corrective-4- in all denominations of the quotient and dividend counters (see Fig.411), thus a total correction of 6 is added at steps 14 and 15.

Step 16.-The pulse from gate 10(16B) switches on the trigger I22, which,via line 92, renders ihoperativethe tubes V5! in the dividend counterand the corresponding tubes in the quotient counter, so that during thesubsequent addition of 10, the carry trigger stage will not be set up(see Carry Suppression, Fig. 4a).

Steps 1? and 18.Dur ing these two steps, a total of 10' is added (seeFig. 4a) into all denominations of both the quotient and dividendcounters, 2 being added by a pulse on line 101 and 8 by a pulse-on line93. This addition takes place in those denominations of the dividend inwhich the carry trigger stage has been set, and in those denominationsof the quotient in which the carry trigger stage has not been set.

Step 19.A pulse on line I82 via cathode follower stage 63 and line 64effects the entry of a carry (see Carry Pulse QUOT, Fig. 4a) in thestage next higher to that in which the carry trigger stage has been setin the quotient counter. The pulse on line I82 also switches off" thetrigger stage I22 (see Carry Suppression, Fig. 4a.) which prevents whileit is on, the switching on of the carry trigger stage via tubes V51 inthe dividend counter and corresponding tubes in the quotient counter.

Step 20.-The pulse from the gate i8'(20B) via the cathode follower stage63 and line 94 causes resetting (see Fig. 4a) of the carry triggerstages in the divisor, dividend and quotient counters. The same pulsevia line 21, amplifier 2B, and gate 24 and line 28, is transmitted tothe start unit It (see Pulse to start Unit, Fig. 4a) to thus switch onemitter stage 1(1) nd start a new long cycle of emitter operation. Thetrigger stage '54 is also switched ofi by the pulse on line 21 and inswitching off transmits a pulse via line 51 to the cycle counter 8 toenter a further 1. This only occurs on the first cycle of the secondhalf of the operation, since trigger stage 54 is only switched on whenswitch unit 13 is switched on.

Similar emitter cycles then occur successively until the number ofcycles in the second half 'of the operation equals that in the firsthalf. A pulse from the cycle counter 8 (Figure la) then sent via line 2|(Figs. 1a and 1) to the start unit I5 to switch it oh to prevent furtheremitter cycles and thus terminate division.

In order to further clarify the method of operation of the machine, anumerical example is shown, together with the values which areregistered on the various counters during each of the emitter cycles.The example considered is that of dividing 121 by 71.

FIRST HALF Number of Emitter Cycles Divisor 1 Overflow indication.

SECOND HALF Divi- 4 Emitter E Divisor dend Quotient Cycle i 1103204121000 1 I 581632 1 290816 121000 0 z 2 145402 121000 0 i 72704 121000 14 5 72704 Q 48296 7 30302 48290 2 5 12170 30352 3 l 2856 a 4544 2856 26a, 2272 2350 52 9 2272 53 l 584 1130 584 10s 10 1 568 584 212 11 Whilethere have been shown and described and pointed out the fundamentalnovel features of the invention as applied to a preferred embodiment, itwill be understood that various omissions and substitutions and changesin the form and details of the device illustrated and in its opera} tionmay be made by those skilled in the art, without departing from thespirit of the invention. It is the intention, therefore, to be limitedonly as indicated by the scope of the following claims.

What is claimed is:

1. An electronic emitter comprising a chain; of electronic triggers,means initiating sequential individual reversing operation of saidtriggers in seriatim, means continuously and automatically interruptingthe seriatim operation at an intermediate point in the chain andautomatically initiating a new interrupted cycle of operation, and meansfor selectively conditioning one of said triggers whereby the length ofthe operative chain is selectively automatically alterable from saidinterrupted series to a complete chain of operation.

2. An electronic device comprising a chain of a chosen number ofelectron valve trigger elements, means initiating sequential individualreversing operation of said trigger elements in seriatim, means forinterrupting the seriatim operation at an intermediate point in thechain, and means for automatically initiating a new seriatim operationof said trigger elements.

3. A device as in claim 2, and including means for automaticallyrepeating said interrupted seriatim operation.

4. A device as in claim 2, and including means for automaticallyrendering said new seriatim operation a second interrupted operation ora complete operation.

5. An electronic device comprising a series of a chosen number ofelectron valve circuits, means initiating sequential individualreversing operation of said circuits in seriatim, and means forautomatically selectively controlling said seriatim operation to includeeither selective seriatim operation of all said circuits or of less thansaid chosen number.

6. A device as in claim 5, and means automatically controlling therespective seriatim operations to automatically selectively include anychosen pattern of full number and less than full number seriatimoperation.

WILLIAM WOODS-IHLL. DAVID THOMAS DAVIS.

REFERENCES CITED The following references are of record in the file ofthis patent:

UNITED STATES PATENTS Number Name Date 2,524,123 Dickinson Oct. 3, 19502,536,917 Dickinson Jan. 2, 1951 2,560,968 MacSorley July 1'7, 19512,562,591 Wagner et al July 31, 1951 FOREIGN PATENTS Number Country Date583,266 Great Britain Dec. 13, 1946

